Field-programmable gate arrays (FPGAs) are configurable integrated circuits (ICs). An FPGA is typically constituted by an arrangement of tiles each including a logic block (LB) configured to output logic information and a switch block (SB) that connects LBs in a predetermined manner. Circuits constituting LBs and SBs include configuration memories, and the contents of the configuration memories can be rewritten to achieve a desired logic by an FPGA as a whole.
If dynamic reconfiguration, which is rewriting to configuration memories at a speed higher than the operating frequency of an FPGA, is possible, a large logic that is normally calculated by FPGAs can be calculated by a single FPGA. In practice, owing to constraints on the speed of writing to memory devices and on the power consumption of memory devices in writing data, it is difficult to conduct such high-speed rewriting to configuration memories as described above.
An existing dynamically reconfigurable FPGA has achieved a function equivalent to dynamic reconfiguration by including multiple configuration memories (multi-context memories) in which data have been written and switching reading from the multi-context memories at a higher speed than the operating frequency of the FPGA. Hereinafter, the number of configuration memories will be referred to as the number of contexts, and the number of a configuration memory to which a memory is switched will be referred to a context. In addition, a dynamically reconfigurable FPGA including multiple configuration memories in which data have been written will be referred to as a multi-context dynamically reconfigurable FPGA (MC-DPGA).
An MC-DPGA is subjected to constraints in implementation of functions different from those imposed on a normal FPGA. For implementing sequential circuits, blocks in an FPGA need to be implemented in such a manner that computations in circuits will be conducted in an appropriate sequence. When the blocks are implemented so that computations are conducted in an appropriate sequence, however, the frequencies of use of the blocks may vary and the effects of the MC-DPGA may not be sufficiently produced. Furthermore, circuits such as ring oscillators resulting in asynchronous circuits owing to a feedback occurring between circuits cannot be applied to dynamic reconfiguration.
It is difficult to provide the advantages of an MC-DPGA with a logic circuit including such circuits. In contrast, a basic tile constituted only by multi-context memories has a larger area than a basic tile constituted only by normal memories as a result of additional memories and an additional control circuit. Thus, the resulting area of the MC-DPGA may become larger when the advantages of the dynamic reconfiguration cannot be achieved.